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_______________________________________________________________ maxim integrated products 1 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. high-efficiency, 8a, current-mode synchronous step-down switching regulator with vid control MAX15109 general description the MAX15109 high-efficiency, current-mode, synchro - nous step-down switching regulator with integrated power switches deliver up to 8a of output current. this regulator operates from 2.7v to 5.5v and provides four output voltages using two vid control inputs. this ic utilizes a current-mode control architecture with a high gain transconductance error amplifier. the current-mode control architecture facilitates easy compensation design and ensures cycle-by-cycle current limit with fast response to line and load transients. this regulator offers skip-mode functionality to reduce current consumption and achieve a higher efficiency at light loads. the low r ds(on) integrated switches ensure high efficiency at heavy loads while minimizing critical inductance, making the layout design a much simpler task with respect to discrete solutions. the high switching frequency (1mhz), along with the pwm current-mode archi - tecture allows for a compact, all-ceramic capacitor design. the ic features a capacitor-programmable slew-rate control to reduce input current at the startup and when the output changes state under vid control. internal control circuitry ensures safe-startup into a prebiased output. power sequencing is controlled with the enable input and power-good output. the ic is available in a 20-bump (4 x 5 array), 2.5mm x 2mm, wlp package and is fully specified over the -40 n c to +85 n c temperature range. applications distributed power systems ddr memory notebook power features s continuous 8a output current s efficiency over 90% s 1% accuracy over load, line, and temperature s operates from a 2.7v to 5.5v supply s vid control inputs for selecting output voltage s programmable slew-rate control s safe startup into prebiased output s 1mhz switching frequency s stable with low-esr ceramic output capacitors s enable input and power-good output for power- supply sequencing s cycle-by-cycle overcurrent protection faults s fully protected against overcurrent and overtemperature s input undervoltage lockout s 20-bump (4 x 5 array), 2.5mm x 2mm, wlp package 19-5918; rev 0; 6/11 + denotes a lead(pb)-free/rohs-compliant package. ordering information typical operating circuit part temp range pin-package MAX15109ewp+ -40 n c to +85 n c 20 wlp vid0 2.7v to 5.5v MAX15109 vid1 vid0 vid1 in lx pgnd fb comp output inx pgood ss
high-efficiency, 8a, current-mode synchronous step-down switching regulator with vid control MAX15109 2 ______________________________________________________________________________________ in, pgood to pgnd .............................................. -0.3v to +6v lx to pgnd ................................................ -0.3v to (v in + 0.3v) lx to pgnd ..................................... -1v to (v in + 0.3v) for 50ns en, comp, fb, ss, vid0, vid1 to pgnd ......................................... -0.3v to (v in + 0.3v) lx current (note 1) ............................................... -12a to +12a output short-circuit duration .................................... continuous continuous power dissipation (t a = +70 n c) wlp (derate 21.3mw/ n c above t a = +70 n c) .......... 745.5mw operating temperature range .......................... -40 n c to +85 n c operating junction temperature (note 2) ...................... +105 n c storage temperature range ............................ -65 n c to +150 n c soldering temperature (reflow) (note 3) ........................ +260 n c electrical characteristics (v in = 5v, c ss = 4.7nf, t a = t j = -40 n c to +85 n c. typical values are at t a = +25 n c, unless otherwise noted.) (note 4) absolute maximum ratings note 1: lx has internal clamp diodes to pgnd and in. do not exceed the power dissipation limits of the device when forward biasing these diodes. note 2: limit the junction temperature to +105 n c for continuous operation at full current. note 3: the wlp package is constructed using a unique set of package techniques that impose a limit on the thermal profile the device can be exposed to during board-level solder attach and rework. this limit permits only the use of the solder pro - files recommended in the industry-standard specification jedec 020a, paragraph 7.6, table 3 for ir/vpr and convection reflow. preheating is required. hand or wave soldering is not allowed. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. parameter symbol conditions min typ max units in voltage range v in 2.7 5.5 v in shutdown supply current v en = 0v 0.3 3 f a in supply current i in v en = 5v, v fb = 1v, not switching 3.4 6 ma v in undervoltage lockout threshold lx starts switching, v in rising 2.6 2.7 v v in undervoltage lockout hysteresis lx stops switching, v in falling 200 mv error amplifier transconductance g mv 1.4 ms voltage gain a vea 90 db output voltage accuracy v fb over line, load, and temperature -1 +1 % fb input bias current i fb -100 +100 na comp to current-sense transconductance g mod 25 a/v comp clamp low v fb = 0.68v 0.93 v compensation ramp valley 1 v power switches high-side switch current-limit threshold i hscl 14 a low-side switch sink current-limit threshold 14 a low-side switch source current-limit threshold 14 a
high-efficiency, 8a, current-mode synchronous step-down switching regulator with vid control MAX15109 _______________________________________________________________________________________ 3 electrical characteristics (continued) (v in = 5v, c ss = 4.7nf, t a = t j = -40 n c to +85 n c. typical values are at t a = +25 n c, unless otherwise noted.) (note 4) note 4: specifications are 100% production tested at t a = +25 n c. limits over the operating temperature range are guaranteed by design and characterization. parameter symbol conditions min typ max units lx leakage current v en = 0v 10 f a rms lx output current 8 a oscillator switching frequency f sw 850 1000 1150 khz maximum duty cycle d max 94 % minimum controllable on-time 100 ns enable en input high threshold voltage v en rising 1.3 v en input low threshold voltage v en falling 0.4 v en input leakage current v en = 5v 1 f a vid control inputs vid_ high threshold voltage v vid_ rising 0.67 v vid_ low threshold voltage v vid_ falling 0.33 v vid1 input leakage current v vid1 = 5v 30 f a vid0 input leakage current v vid0 = 5v 1 f a soft-start, prebias soft-start current i ss v ss = 0.45v, sourcing 10 f a ss discharge resistance r ss i ss = 10ma, sinking 8.5 i ss prebias mode stop voltage ss rising 0.58 v hiccup number of consecutive current-limit events to hiccup 8 events timeout 1024 clock cycles power-good output pgood threshold pgt fb rising vid0 vid1 mv 0 0 824 853 884 0 1 705 729 755 1 0 654 677 701 1 1 580 602 624 fb falling 559 578 600 mv pgood v ol i pgood = 5ma, v fb = 0.5v 22 100 mv pgood leakage v pgood = 5v, v fb = 0.68v 1 f a thermal shutdown thermal shutdown threshold +160 n c thermal shutdown hysteresis temperature falling 25 n c
high-efficiency, 8a, current-mode synchronous step-down switching regulator with vid control MAX15109 4 ______________________________________________________________________________________ typical operating characteristics (circuit of typical application circuit , t a = +25 n c, unless otherwise noted.) efficiency vs. output current (v in = 5v) MAX15109 toc01 output current (a) efficiency (%) 7 6 4 5 2 3 1 10 20 30 40 50 60 70 80 90 100 0 0 8 v out = 0.675v v out = 0.725v v out = 0.9v v out = 0.8v output voltage vs. supply voltage (v out = 0.675v) MAX15109 toc03b supply voltage (v) output voltage (v) 5.1 4.7 4.3 3.9 3.5 3.1 0.665 0.670 0.675 0.680 0.685 0.690 0.660 2.7 5.5 8a load 4a load output voltage vs. output current (v out = 0.675v) MAX15109 toc04b output current (a) 7 6 5 4 3 2 1 0 8 v in = 3.3v v in = 5v output voltage (v) 0.665 0.670 0.675 0.680 0.685 0.690 0.660 output voltage vs. output current (v out = 0.9v) MAX15109 toc04a output current (a) 7 6 5 4 3 2 1 0 8 output voltage (v) 0.890 0.895 0.900 0.905 0.910 0.915 0.885 v in = 3.3v v in = 5v output voltage error vs. supply voltage MAX15109 toc05 supply voltage (v) 5.1 4.7 4.3 3.9 3.5 3.1 -0.50 -0.40 -0.30 -0.20 -0.10 0 -0.60 2.7 5.5 v out = 0.9v v out = 0.675v i load = 8a output voltage error (%) efficiency vs. output current (v in = 3.3v) MAX15109 toc02 output current (a) efficiency (%) 7 6 4 5 2 3 1 10 20 30 40 50 60 70 80 90 100 0 0 8 v out = 0.675v v out = 0.725v v out = 0.9v v out = 0.8v output voltage vs. supply voltage (v out = 0.9v) MAX15109 toc03a supply voltage (v) output voltage (v) 5.1 4.7 4.3 3.9 3.5 3.1 0.890 0.895 0.900 0.905 0.910 0.915 0.885 2.7 5.5 8a load 4a load
high-efficiency, 8a, current-mode synchronous step-down switching regulator with vid control MAX15109 _______________________________________________________________________________________ 5 typical operating characteristics (continued) (circuit of typical application circuit , t a = +25 n c, unless otherwise noted.) load-transient response (v in = 5v, v out = 0.9v) MAX15109 toc06 v out 10mv/div ac-coupled i out 4a 2a 40s/div switching waveform in skip mode (i out = 10ma, v in = 5v) MAX15109 toc08 v out 10mv/div ac-coupled 40s/div i lx 2a /div v lx 5v/div MAX15109 toc10a v en 2v/div v out 500mv/div v pgood 5v/div v lx 5v/div 200s/div soft-start waveforms (no load, skip mode) switching waveforms (i out = 8a, v in = 5v) MAX15109 toc07 v out 10mv/div ac-coupled i lx 5a/div v lx 5v/div 400ns /div shutdown waveform (i load = 8a) MAX15109 toc09 v en 2v/div v out 500mv/div v pgood 2v/div v lx 5v/div i lx 5a/div 10s/div MAX15109 toc10b v en 2v/div v out 500mv/div v pgood 5v/div v lx 5v/div 200s/div soft-start waveforms (i load = 8a)
high-efficiency, 8a, current-mode synchronous step-down switching regulator with vid control MAX15109 6 ______________________________________________________________________________________ typical operating characteristics (circuit of typical application circuit , t a = +25 n c, unless otherwise noted.) MAX15109 toc11a 0.9v 0.8v 0.725v 0.675v v out 50mv/div 40s/div 0.675v vid transitions (v in = 3.3v, i out = 8a) MAX15109 toc11c 0.9v 0.675v 0.725v 0.8v v out 50mv/div 40s/div 0.8v vid transitions (v in = 3.3v, i out = 8a) input shutdown current vs. supply voltage MAX15109 toc12 supply voltage (v) input shutdown current (a) 0.4 0.8 1.2 1.6 2.0 0 5.1 4.7 3.9 4.3 3.5 3.1 2.7 5.5 MAX15109 toc11b 0.9v 0.8v 0.675v 0.725v v out 50mv/div 40s/div 0.725v vid transitions (v in = 3.3v, i out = 8a) MAX15109 toc11d 0.8v 0.675v 0.725v 0.9v v out 50mv/div 40s/div 0.9v vid transitions (v in = 3.3v, i out = 8a) input current vs. input voltage MAX15109 toc13 input voltage (v) input current (ma) 1.0 2.0 3.0 4.0 5.0 0 5.1 4.7 3.9 4.3 3.5 3.1 2.7 5.5 no load
high-efficiency, 8a, current-mode synchronous step-down switching regulator with vid control MAX15109 _______________________________________________________________________________________ 7 typical operating characteristics (continued) (circuit of typical application circuit , t a = +25 n c, unless otherwise noted.) MAX15109 toc14 v out 500mv/div 400s/div short-circuit hiccup mode i in 2a /div i out 10a /div fb voltage vs. temperature (v out = 0.9v) MAX15109 toc16 temperature (c) fb voltage (v) 60 35 10 -15 0.890 0.895 0.900 0.905 0.910 0.915 0.885 -40 65 no load v in = 3.3v v in = 5v MAX15109 toc18 v out 500mv/div 200s/div enable into prebiased 0.5v output (8a load) v en 2v/div i lx 5a/div v pgood 2v/div rms input current vs. supply voltage MAX15109 toc15 supply voltage (v) rms input current (a) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 5.1 4.7 3.9 4.3 3.5 3.1 2.7 5.5 short-circuit on outpu t MAX15109 toc17 v out 500mv/div 100s/div soft-start waveforms (external refin) v ss 500mv/div v pgood 2v/div MAX15109 toc19 v out 500mv/div 200s/div enable into prebiased 0.5v output (no load) v en 2v/div i lx 2a/div v pgood 2v/div
high-efficiency, 8a, current-mode synchronous step-down switching regulator with vid control MAX15109 8 ______________________________________________________________________________________ pin description pin configuration bump name function a1, b1, c1, d1 pgnd power ground. low-side switch source terminal. connect pgnd and the return terminals of input and output capacitors to the power ground plane. a2, a3, b2, c2 lx inductor connection. connect lx to the switching side of the inductor. lx is high impedance when the device is in shutdown mode. a4 pgood open-drain power-good output. pgood goes low when v fb is below the pgood threshold. a5 vid0 vid0 logic input. use vid0 and vid1 to select output voltage. b3, c3, d3 in input power supply. input supply range is 2.7v to 5.5v. bypass in with a minimum 10 f f ceramic capacitor to pgnd. see the typical application circuit. b4 i.c. internally connected. leave unconnected. b5 fb feedback input. connect fb to the sense the output voltage. c4 vid1 vid1 logic input. use vid0 and vid1 to select output voltage. c5 ss soft-start and vid transition timing control. connect a capacitor from ss to pgnd to set the startup time and the output voltage transition timing. see the output voltage transition timing section for details. d2 inx internally unconnected. inx is not internally connected to in. however, do externally connect inx to in to increase the area of the power plane for optimal heat dissipation. d4 en enable input. en is a digital input that turns the regulator on and off. drive en high to turn on the regulator. connect to in for always-on operation. d5 comp error amplifier output. connect compensation network from comp to signal ground (sgnd). see the compensation design guidelines section. wlp bottom view 5 4 3 2 1 b c d a MAX15109 vid0 pgood lx lx pgnd fb i.c. in lx pgnd ss vid1 in lx pgnd comp en in inx pgnd
high-efficiency, 8a, current-mode synchronous step-down switching regulator with vid control MAX15109 _______________________________________________________________________________________ 9 functional diagram 10a MAX15109 ss en fb ground sense buffer error amplifier comp 0.58v vid0 vid1 strong prebias forced_start ck ss buffer c ramp ck oscillator control logic in in lx lx ramp gen in current-sense amplifier high-side current limit low-side source-sink current limit and zero-crossing comparator sink source pgood zx v pgt , v pgh power-good comparator voltage reference vid control bias generator en logic, in uvlo thermal shdn shdn v ref in inx lx pgnd
high-efficiency, 8a, current-mode synchronous step-down switching regulator with vid control MAX15109 10 _____________________________________________________________________________________ detailed description the MAX15109 high-efficiency, current-mode switch - ing regulator delivers up to 8a of output current. the regulator operates from 2.7v to 5.5v and provides a vid selectable output. the ic current-mode control architecture uses a high gain transconductance error amplifier that facilitates an easy compensation design and ensures cycle-by-cycle current limit with fast response to line and load transients. the regulator features a 1mhz fixed switching fre - quency, allowing for all-ceramic capacitor designs with fast transient responses. the high operating frequency minimizes the size of external components. the ic is available in a 2.5mm x 2mm (4 x 5 array), 0.5mm pitch wlp package. the regulator offers skip-mode functionality to reduce current consumption and achieve a high efficiency at light output loads. the low r ds(on) integrated switches ensure high efficiency at heavy loads while minimizing critical inductance, making the layout design a much simpler task than that of discrete solutions. the ics simple layout and footprint assure first-pass success in new designs. the ic has output voltages of 0.9v, 0.8v, 0.725v, and 0.625v by configuring the vid inputs. the regulator offers capacitor-programmable soft-start to reduce input inrush current. the device safely starts up into a prebi - ased output. the ic includes an enable input and open- drain pgood output for sequencing with other devices. controller function pwm logic the controller logic block determines the duty cycle of the high-side mosfet under different line, load, and temperature conditions. under normal operation, where the current-limit and temperature protection are not trig - gered, the controller logic block takes the output from the pwm comparator to generate the driver signals for both high-side and low-side mosfets. the control logic block controls the break-before-make logic and all the necessary timing. the high-side mosfet turns on at the beginning of the oscillator cycle and turns off when the comp voltage crosses the internal current-mode ramp waveform. the internal ramp is the sum of the compensation ramp and the current-mode ramp. the high-side mosfet also turns off if the maximum duty cycle exceeds 95%, or when the current limit is reached. the low-side mosfet turns on for the remainder of the switching cycle. starting into a prebiased output the ic can soft-start into a prebiased output with - out discharging the output capacitor. in safe prebi - ased startup, both low-side and high-side mosfets remain off to avoid discharging the prebiased out - put. pwm operation starts when the voltage on ss crosses the voltage on fb. the ic can start into a prebiased voltage higher than the nominal set point without abruptly discharging the out - put. forced pwm operation starts when the ss voltage reaches 0.58v, forcing the converter to start. when the low-side sink current-limit threshold of 14a is reached, the low-side switch turns off before the end of the clock period. the low-side sink current limit is 14a. the high- side switch turns on until one of the following conditions is satisfied: ? high-side source current hits the reduced high-side current limit (14a). the high-side switch turns off for the remaining time of clock period. ? the clock period ends. reduced high-side current limit is activated in order to recirculate the current into the high-side power switch rather than into the internal high-side body diode, which can cause damage to the devices. the high-side current limit is set to 14a. low-side sink current limit protects the low-side switch from excessive reverse current during prebiased operation. enable input the ic features independent device enable control and power-good signal that allow for flexible power sequenc - ing. drive the enable input (en) high to enable the regulator, or connect en to in for always-on operation. power-good (pgood) is an open-drain output that goes high when v fb is above the pgood threshold, and goes low if v fb is below the pgood threshold.
high-efficiency, 8a, current-mode synchronous step-down switching regulator with vid control MAX15109 ______________________________________________________________________________________ 11 programmable soft-start (ss) the ic utilizes a soft-start feature to slowly ramp up the regulated output voltage to reduce input inrush current during startup. connect a capacitor from ss to pgnd to set the startup time. see the output voltage transition timing section for capacitor selection details. error amplifier a high-gain error amplifier provides accuracy for the voltage feedback loop regulation. connect a compen - sation network between comp and sgnd. see the compensation design guidelines section. the error amplifier transconductance is 1.4ms. comp clamp low is set to 0.8v, just below the pwm ramp compensation valley, helping comp to rapidly return to the correct set point during load and line transients. pwm comparator the pwm comparator compares comp voltage to the current-derived ramp waveform (lx current to comp voltage transconductance value is 25a/v). to avoid instability due to subharmonic oscillations when the duty cycle is around 50% or higher, a compensation ramp is added to the current-derived ramp waveform. the compensation ramp slope (0.3v x 1mhz = 0.3v/ f s) is equivalent to half of the inductor current down-slope in the worst case (load 2a, current ripple 30% and maxi - mum duty-cycle operation of 95%). the compensation ramp valley is set to 1v. overcurrent protection and hiccup when the converter output is connected to ground or the device is overloaded, each high-side mosfet current- limit event (14a) turns off the high-side mosfet and turns on the low-side mosfet. a 3-bit counter incre - ments on each current-limit event. the counter is reset after three consecutive events of high-side mosfet turn-on without reaching the current limit. if the current- limit condition persists, the counter fills up reaching eight events. the control logic then discharges ss, stops both high-side and low-side mosfets and waits for a hiccup period (1024 clock cycles) before attempting a new soft- start sequence. the hiccup-mode also operates during soft-start. thermal shutdown protection the ic contains an internal thermal sensor that limits the total power dissipation to protect it in the event of an extended thermal fault condition. when the die tempera - ture exceeds +160 n c, the thermal sensor shuts down the device, turning off the dc-dc converter to allow the die to cool. after the die temperature falls by 25 n c, the device restarts, following the soft-start sequence. skip mode operation the ic operates in skip mode. when in skip mode, lx output becomes high impedance when the inductor current falls below 0.7a. the inductor current does not become negative. during a clock cycle, if the inductor current falls below the 0.7a threshold (during off-time), the low side turns off. at the next clock cycle, if the output voltage is above the set point the pwm logic keeps both high-side and low-side mosfets off. if instead the output voltage is below the set point, the pwm logic drives the high-side on for a minimum fixed on-time (330ns). in this way, the system skips cycles, reducing the frequency of operations, and switches only as needed to service load at the cost of an increase in output-voltage ripple. see the skip mode frequency and output ripple section for details. in skip mode, power dissipation is reduced and efficiency improved at light loads because the internal power mosfets do not switch at every clock cycle.
high-efficiency, 8a, current-mode synchronous step-down switching regulator with vid control MAX15109 12 _____________________________________________________________________________________ applications information setting the output voltage the output voltage is selected by using the vid0 and vid1 control inputs. table 1 summarizes the output voltages. inductor selection a large inductor value results in reduced inductor ripple current, leading to a reduced output ripple voltage. a high-value inductor is of a larger physical size with a higher series resistance (dcr) and a lower saturation current rating. choose inductor values to produce a ripple current equal to 30% of the load current. choose the inductor with the following formula: out out sw l in v v l 1- f i v ? ? = ? ? ? ? ? where f sw is the internally fixed 1mhz switching fre - quency, and d i l is the estimated inductor ripple current (typically set to 0.3 x i load ). in addition, the peak induc - tor current, i l_pk , must always be below the high-side current-limit value, i hscl , and the inductor saturation current rating, i l_sat . ensure that the following relationship is satisfied: l_pk load l hscl l_sat 1 i i i min(i ,i ) 2 = + ? < input capacitor selection for a step-down converter, the input capacitor c in helps to keep the dc input voltage steady, in spite of discon - tinuous input ac current. use low-esr capacitors to minimize the voltage ripple due to esr. size c in using the following formula: load out in sw in_ripple in i v c f v v = ? figure 1. peak current-mode regulator transfer model table 1. output voltages l control logic v comp v out pwm comparator comp r c r out g mv v in power modulator output filter and load note: the g mod stage shown above models the average current o f the inductor injected into the output load. this represents a simplification for the power modulator stage drawn above . error amplifier feedback divider compensation ramp g mc dcr i l v out v out i l esr c out r load c c ss *c cc is optional. r out = a vea /g mv *c cc fb g mod c q hs q ls vid0 vid1 voltage (v) 0 0 0.9 0 1 0.8 1 0 0.725 1 1 0.675
high-efficiency, 8a, current-mode synchronous step-down switching regulator with vid control MAX15109 ______________________________________________________________________________________ 13 make sure that the selected capacitance can accom - modate the input ripple current given by: out in out rms o in v (v - v ) i i v = if necessary, use multiple capacitors in parallel to meet the rms current rating requirement. output capacitor selection use low-esr ceramic capacitors to minimize the voltage ripple due to esr. use the following formula to estimate the total output voltage peak-to-peak ripple: out out out esr_cout sw in sw out v v 1 v 1- r f l v 8 f c ? ? ? ? ? = + ? ? ? ? ? ? ? ? select the output capacitors to produce an output ripple voltage that is less than 2% of the set output voltage. output voltage transition timing the ic features programmable output voltage transition timing control. the regulator tracks the voltage on the ss pin that is set with a current-limited (10a) vid dac. a small capacitor at ss can therefore be used to set the transition timing for startup and vid transitions. ss ss out i x t c v ? = ? where i ss is the soft-start current of 10 f a, v out is the output-voltage transition, and t is the transition time. when using large c out capacitance values, the high- side current limit can trigger during the soft-start period. to ensure the correct soft-start time, t ss , choose c ss large enough to satisfy: out ss ss out hscl_min out fb v i c c (i - i ) v >> = i hscl_min is the minimum high-side switch current-limit value. skip mode frequency and output ripple in skip mode, the switching frequency (f skip ) and output ripple voltage (v out-ripple ) shown in figure 3 are cal - culated as follows: t on is a fixed time by design (330ns, typ); the peak inductor current reached is: in out skip limit on v v i t 2av ? ? = t off1 is the time needed for the inductor current to reach the zero-crossing (~0a): skip-limit off1 out l i t v = during t on and t off1 , the output capacitor stores a charge equal to: ( ) 2 skip-limit load in out out out 1 1 l i - i v - v v q 2 ? ? + ? ? ? ? ? = during t off2 (= n x t ck , number of clock cycles skipped), the output capacitor loses this charge: out off2 load q t i ? = ( ) 2 skip-limit load in out out off2 load 1 1 l i - i v - v v t 2 i ? ? + ? ? ? ? = finally, frequency in skip mode is: skip on off1 off2 1 f t t t = + + output ripple in skip mode is: ( ) ( ) out-ripple cout-ripple esr-ripple skip-limit load on esr,cout skip-limit load out v v v i - i t r i - i c = + = + ( ) ( ) out-ripple skip-limit esr,cout skip-limit load out in out v l i r i - i c v - v = ? ? + ? ? ? ? ? ? size c out based on the above formula to limit output ripple in skip mode. figure 2. setting soft-start time MAX15109 c ss r ss v ref_ext ss
high-efficiency, 8a, current-mode synchronous step-down switching regulator with vid control MAX15109 14 _____________________________________________________________________________________ compensation design guidelines the ic uses a fixed-frequency, peak-current-mode con - trol scheme to provide easy compensation and fast tran - sient response. the inductor peak current is monitored on a cycle-by-cycle basis and compared to the comp voltage (output of the voltage error amplifier). the regu - lators duty cycle is modulated based on the inductors peak current value. this cycle-by-cycle control of the inductor current emulates a controlled current source. as a result, the inductors pole frequency is shifted beyond the gain bandwidth of the regulator. system stability is provided with the addition of a simple series capacitor-resistor from comp to pgnd. this pole-zero combination serves to tailor the desired response of the closed-loop system. the basic regulator loop consists of a power modulator (comprising the regulators pulse- width modulator, compensation ramp, control circuitry, mosfets, and inductor), the capacitive output filter and load, an output feedback, and a voltage-loop error amplifier with its associated compensation circuitry. see figure 1. the average current through the inductor is expressed as: l mod comp i g v = where i l is the average inductor current and g mod is the power modulators transconductance. for a buck converter: out load l v r i = where r load is the equivalent load resistor value. combining the above two relationships, the power mod - ulators transfer function in terms of v out with respect to v comp is: load l fb load mod comp l mod r i v r g v i g = = having defined the power modulators transfer function gain, the total system loop gain can be written as follows (see figure 1): ( ) ( ) ( ) ( ) ( ) out c c c cc c out c cc c out r sc r 1 s c c r r 1 s c || c r || r 1 + = ? ? + + + ? ? ? ? ? ? out mod load out load sc esr 1 g r sc esr r 1 + = ? ? ? ? 2 vea 1 2 out r a gain r r r = where r out is the quotient of the error amplifiers dc gain, a vea , divided by the error amplifiers transconduc - tance, g mv ; r out is much larger than r c . 2 fb 1 2 out r v r r v = + also, c c is much larger than c cc , therefore: c cc c c c c + and c cc cc c || c c rewriting: ( ) ( ) ( ) ( ) c c fb vea out vea c cc c mv out mod load out load sc r 1 v gain a v a sc 1 sc r 1 g sc esr 1 g r sc esr r 1 + = ? ? ? ? + + ? ? ? ? ? ? ? ? ? ? ? ? ? ? the dominant poles and zeros of the transfer loop gain are shown below: mv p1 avea_db/20 c g f 2 10 c = p2 out load 1 f 2 c esr r = + p3 cc c 1 f 2 c r = z1 c c 1 f 2 c r = z2 out 1 f 2 c esr =
high-efficiency, 8a, current-mode synchronous step-down switching regulator with vid control MAX15109 ______________________________________________________________________________________ 15 the order of pole-zero occurrence is: p1 p2 z1 z2 p3 f f f f f < < < under heavy load, f p2 , approaches f z1 . a graphical representation of the asymptotic system closed-loop response, including dominant pole and zero locations is shown in figure 3. if c out is large, or exhibits a lossy equivalent series resistance (large esr), the circuits second zero might come into play around the crossover frequency (f co = /2 g ). in this case, a third pole can be induced by a second (optional) small compensation capaci - tor (c cc ), connected from comp to pgnd. the loop responses fourth asymptote (in bold, figure 4) is the one of interest in establishing the desired crossover fre - quency (and determining the compensation component values). a lower crossover frequency provides for stable closed-loop operation at the expense of a slower load and line transient response. increasing the crossover frequency improves the transient response at the (poten - tial) cost of system instability. a standard rule of thumb sets the crossover frequency p 1/10th of the switching frequency. first, select the passive and active power components that meet the applications requirements. then, choose the small-signal compensation compo - nents to achieve the desired closed-loop frequency response and phase margin as outlined in the closing the loop: designing the compensation circuitry section . closing the loop: designing the compensation circuitry select the desired crossover frequency. choose f co approximately 1/10th of the switching frequency f sw , or f co 100khz. select r c using the transfer-loops fourth asymptote gain (assuming f co > f p1 , f p2 , and f z1 and setting the overall loop gain to unity) as follows: ( ) fb mv c mod load out co out load v 1 g r g r v 1 2 f c esr r = + therefore: ( ) co out load out c fb mv mod load 2 f c esr r v r v g g r + = for r load much greater than esr, the equation can be further simplified as follows: out co out c fb mv mod v 2 f c r v g g = where v fb is equal to 0.6v. determine c c by selecting the desired first system zero, f z1 , based on the desired phase margin. typically, set - ting f z1 below 1/5th of f co provides sufficient phase margin. co z1 c c f 1 f 2 c r 5 = therefore: c co c 5 c 2 f r figure 3. skip-mode waveforms i l v out i skip-limit t on t off1 t off2 = n x t ck i load v out-ripple
high-efficiency, 8a, current-mode synchronous step-down switching regulator with vid control MAX15109 16 _____________________________________________________________________________________ if the esr output zero is located at less than one-half the switching frequency, use the (optional) secondary compensation capacitor, c cc , to cancel it, as follows: p3 z2 cc c out 1 1 f f 2 c r 2 c esr = = = therefore: out cc c c esr c r = if the esr zero exceeds 1/2 the switching frequency, use the following equation: sw p3 cc c f 1 f 2 c r 2 = = therefore: cc sw c 2 c 2 f r = overall c cc detracts from the overall system phase margin. place this third pole well beyond the desired crossover frequency to minimize the interaction with the system loop response at crossover. ignore c cc in these calculations if c cc is smaller than 10pf. power dissipation the ic is available in a 20-bump wlp package and can dissipate up to 745.5mw at t a = +70 n c. when the die temperature exceeds +160 n c, the thermal-shutdown protection is activated. see the thermal shutdown protection section. figure 4. asymptotic loop response of peak current-mode regulator 1st asymptote v fb x v out -1 x 10 a vea [db]/20 x g mod x r load 2nd asymptote v fb x v out -1 x g mv x (c c ) -1 x g mod x r load 3rd asymptote v fb x v out -1 x g mv x (c c ) -1 x g mod x r load x (c out (esr + r load )) -1 4th asymptote v fb x v out -1 x g mv x r c x g mod x r load x (c out (esr + r load )) -1 5th asymptote v fb x v out -1 x g mv x r c x g mod x (esr || r load ) 6th asymptote v fb x v out -1 x g mv x (c cc ) -1 x g mod x (esr || r load ) unity gain rad/s 3rd pole (c cc r c ) -1 2nd zero (c out esr) -1 1st zero (c c r c ) -1 2nd pole (c out (esr + r load )) -1 1st pole g mv x (10 a vea [db]/20 c c ) -1 co
high-efficiency, 8a, current-mode synchronous step-down switching regulator with vid control MAX15109 ______________________________________________________________________________________ 17 layout procedure careful pcb layout is critical to achieve clean and stable operation. it is highly recommended to duplicate the MAX15109 evaluation kit layout for optimum perfor - mance. if deviation is necessary, follow these guidelines for good pcb layout: 1) connect input and output capacitors to the power ground plane. 2) place bypass capacitors as close to in and the soft- start capacitor as close to ss as possible. 3) keep the high-current paths as short and wide as possible. keep the path of switching current short and minimize the loop area formed by lx, the output capacitors, and the input capacitors. 4) connect in, lx, and pgnd separately to a large copper area to help cool the ic to further improve efficiency. 5) ensure all feedback connections are short and direct. place the feedback resistors and compensa - tion components as close as possible to the ic. 6) route high-speed switching nodes (such as lx) away from sensitive analog areas (such as fb, comp, sgnd, and ss). typical application circuit vid0 2.7v to 5.5v r pull 100ki r ea 2.43ki c ea 6800pf c ea2 100pf r ext_ref 1ki c in2 22f c out2 47f c out1 0.1f c in2 22f c ss 33nf vid1 en in lx pgnd fb comp output l out 0.56h inx pgood ss MAX15109
high-efficiency, 8a, current-mode synchronous step-down switching regulator with vid control MAX15109 18 _____________________________________________________________________________________ chip information process: bicmos package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 20 wlp w202d2z+1 21-0505 refer to application note 1891
high-efficiency, 8a, current-mode synchronous step-down switching regulators with vid control MAX15109 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 19 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 6/11 initial release

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